Principal PLL Design Engineer

From the original posting

Irvine, CA or San Jose, CA Are you a PLL Design Engineer passionate about developing the high-speed clocking technology that will power the next generation of AI infrastructure? Join our fast-growing semiconductor startup and help deliver disruptive High-Speed Interconnect solutions for tomorrow's optical networks. We are seeking a High-Speed CMOS PLL Analog Design Engineer to play a key role in the architecture and design of advanced clocking circuits for next-generation optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems. In this role, you will architect and design…